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| == História == | | == História == |
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| == Design ==
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| == Vantagens == | | == Vantagens == |
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| == Desvantagens == | | == Desvantagens == |
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| | === Altera === |
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| <source lang="VHDL"> | | <source lang="VHDL"> |
| -- (this is a VHDL comment)
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| -- import std_logic from the IEEE library
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| library IEEE;
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| use IEEE.std_logic_1164.all;
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| -- this is the entity
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| entity ANDGATE is
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| port (
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| I1 : in std_logic;
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| I2 : in std_logic;
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| O : out std_logic);
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| end entity ANDGATE;
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|
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| -- this is the architecture
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| architecture RTL of ANDGATE is
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| begin
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| O <= I1 and I2;
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| end architecture RTL;
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| </source> | | </source> |
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| (Notice that <code>RTL</code> stands for ''[[Register transfer level]]'' design.) While the example above may seem verbose to HDL beginners, many parts are either optional or need to be written only once. Generally simple functions like this are part of a larger behavioral module, instead of having a separate module for something so simple. In addition, use of elements such as the <tt>std_logic</tt> type might at first seem to be an overkill. One could easily use the built-in <tt>bit</tt> type and avoid the library import in the beginning. However, using this [[Multi-valued logic|9-valued logic]] ([[IEEE 1164|<tt>U</tt>,<tt>X</tt>,<tt>0</tt>,<tt>1</tt>,<tt>Z</tt>,<tt>W</tt>,<tt>H</tt>,<tt>L</tt>,<tt>-</tt>]]) instead of simple bits (0,1) offers a very powerful simulation and debugging tool to the designer which currently does not exist in any other HDL.
| | === Padrões de Projeto === |
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| === Synthesizable constructs and VHDL templates === | |
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| === MUX template ===
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| The [[multiplexer]], or 'MUX' as it is usually called, is a simple construct very common in hardware design. The example below demonstrates a simple two to one MUX, with inputs <tt>A</tt> and <tt>B</tt>, selector <tt>S</tt> and output <tt>X</tt>. Note that there are many other ways to express the same MUX in VHDL.
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| <source lang="VHDL">X <= A when S = '1' else B;</source>
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| === Latch template ===
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| A [[transparent latch]] is basically one bit of memory which is updated when an enable signal is raised. Again, there are many other ways this can be expressed in VHDL.
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| <source lang="VHDL">
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| -- latch template 1:
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| Q <= D when Enable = '1' else Q;
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| -- latch template 2:
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| process(D,Enable)
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| begin
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| if Enable = '1' then
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| Q <= D;
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| end if;
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| end process;
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| </source>
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| == References == | | == References == |
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| {{Commons category}} | | {{Commons category}} |
| {{wikibooks|Programmable Logic|VHDL}} | | {{wikibooks|Programmable Logic|VHDL}} |
| * [http://www.eda.org/twiki/bin/view.cgi/P1076/WebHome IEEE VASG (VHDL Analysis and Standardization Group)], the official VHDL working group
| | * [http://cseweb.ucsd.edu/classes/sp13/cse140-a/ CSE140: Components and Design Techniques for Digital Systems]. |
| * The VHDL newsgroup ''comp.lang.vhdl'' on [news://comp.lang.vhdl Usenet] and the [http://groups.google.com/group/comp.lang.vhdl/topics web] and their [http://www.vhdl.org/comp.lang.vhdl/ Frequently Asked Questions And Answers]
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| * [http://cseweb.ucsd.edu/classes/sp13/cse140-a/lectures/chap-rtl.pdf Máquinas de Estado de Alto Nível (tips and tricks)]. | |
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| {{DEFAULTSORT:Vhdl}} | | {{DEFAULTSORT:Vhdl}} |
| [[Category:Ada programming language family]] | | [[Category:Ada programming language family]] |
| [[Category:Hardware description languages]] | | [[Category:Hardware description languages]] |
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| <__tonussi> automata, você me perguntou de refs do meu estudo em vhdl, basicamente isso é o que eu consigo fazer de mais alto nível http://cseweb.ucsd.edu/classes/sp13/cse140-a/lectures/chap-rtl.pdf livro para estudar que é ótimo Frank Vahid - Digital Systems (te da uma noção mt boa)
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| [[Category:Lab Macambira]] | | [[Category:Lab Macambira]] |
