VHDL

VHDL (VHSIC Hardware Description Language) is a hardware description language used in electronic design automation to describe digital and mixed-signal systems such as field-programmable gate arrays and integrated circuits. VHDL can also be used as a general purpose parallel programming language.

Desvantagens

<source lang="VHDL"> -- (this is a VHDL comment)

-- import std_logic from the IEEE library library IEEE; use IEEE.std_logic_1164.all;

-- this is the entity entity ANDGATE is

 port ( 
   I1 : in std_logic;
   I2 : in std_logic;
   O  : out std_logic);

end entity ANDGATE;

-- this is the architecture architecture RTL of ANDGATE is begin

 O <= I1 and I2;

end architecture RTL; </source>

(Notice that RTL stands for Register transfer level design.) While the example above may seem verbose to HDL beginners, many parts are either optional or need to be written only once. Generally simple functions like this are part of a larger behavioral module, instead of having a separate module for something so simple. In addition, use of elements such as the std_logic type might at first seem to be an overkill. One could easily use the built-in bit type and avoid the library import in the beginning. However, using this 9-valued logic (U,X,0,1,Z,W,H,L,-) instead of simple bits (0,1) offers a very powerful simulation and debugging tool to the designer which currently does not exist in any other HDL.

MUX template

The multiplexer, or 'MUX' as it is usually called, is a simple construct very common in hardware design. The example below demonstrates a simple two to one MUX, with inputs A and B, selector S and output X. Note that there are many other ways to express the same MUX in VHDL.

<source lang="VHDL">X <= A when S = '1' else B;</source>

Latch template

A transparent latch is basically one bit of memory which is updated when an enable signal is raised. Again, there are many other ways this can be expressed in VHDL.

<source lang="VHDL"> -- latch template 1: Q <= D when Enable = '1' else Q;

-- latch template 2: process(D,Enable) begin

 if Enable = '1' then
   Q <= D;
 end if;

end process; </source>

References

<references> </references>

Further reading

• "Digital Design: With RTL, VHDL, and Verilog" (2nd ed, Wiley, 2010); Plus "VHDL for Digital Design" / "Verilog for Digital Design" (Wiley 2007)

External links

• IEEE VASG (VHDL Analysis and Standardization Group), the official VHDL working group
• The VHDL newsgroup comp.lang.vhdl on Usenet and the web and their Frequently Asked Questions And Answers
• Máquinas de Estado de Alto Nível (tips and tricks).

<__tonussi> automata, você me perguntou de refs do meu estudo em vhdl, basicamente isso é o que eu consigo fazer de mais alto nível http://cseweb.ucsd.edu/classes/sp13/cse140-a/lectures/chap-rtl.pdf livro para estudar que é ótimo Frank Vahid - Digital Systems (te da uma noção mt boa)